1. Field of the Invention
This invention relates to the manufacture of bipolar transistors, and more particularly, to the method of forming the emitter window for a bipolar transistor having self-aligned emitter-base regions.
2. Description of the Prior Art
In the manufacture of bipolar transistors, much is research has been directed to increasing transistor speed. One approach to increasing the speed is by means of the transistor geometry. For high speed bipolar transistors, the two critical dimensions are the emitter stripe width and the base thickness. The emitter stripe width is defined by the lateral dimension of the emitter region, while the base thickness is defined by the vertical dimension of the base region. It is desirable to manufacture transistors with both the emitter strip width and the base thickness as small as possible so as to reduce the base resistance for the reason that base resistance is a major impediment to the speed of a transistor. Moreover, the ratio of the length to the width of the emitter should be as large as possible and since the emitter length is determined by other manufacturing constraints, the emitter stripe width is the only dimension that can be adjusted to reduce the base resistance.
In the manufacture of conventional bipolar transistors, the emitter window which defines the stripe width is located and sized by the use of photolithography. A photolithographic mask is positioned onto a layer of polysilicon which has been epitaxially grown onto a single crystal silicon substrate, and an emitter window is then etched through the polysilicon to expose regions of the single crystal silicon. Experience shows that etching an emitter opening into an extrinsic base polysilicon layer without overetch into an intrinsic base region is very difficult. The photolithographic method for defining the emitter window has a size limitation in that, typically the smallest emitter stripe width that can be obtained is approximately 0.7 microns. In addition, the use of photolithography masking techniques results in inaccuracies due to improper alignment with the intrinsic base resulting in poor reproducibility.
Various techniques have been employed to define the emitter window in an attempt to overcome the prior art deficiencies. In U.S. Pat. No. 4,499,657, photolithography is used to define both the emitter and base windows simultaneously thereby reducing some of the misalignment effects. The emitter stripe width is limited to the range between 0.5 to 2 microns.
U.S. Pat. No. 4,504,332 discloses a self-alignment technique for manufacturing a bipolar transistor. A thermal oxide layer, silicon nitride layer and a boron oxide layer are successively deposited onto a single crystal silicon substrate. Conventional photolithographic techniques are used to etch a window for the formation of both the base and the emitter. A layer of silicon is epitaxially grown over the entire substrate with polysilicon being formed on the insulating layer and single crystal being formed on the exposed region of the substrate. The polysilicon regions are doped to form external base regions. A conformal layer of thermal oxide is deposited over the poly and single crystal silicon regions and the thermal oxide is etched to expose the single crystal. An internal base region is formed by implantation and the emitter region is formed by diffusion from a conformal doped oxide layer. Contact holes are then etched in the oxide layer for the emitter, base and collector. While the emitter and base are self-aligned, the process steps are numerous and complicated. In addition, the emitter window is defined by conventional photolithographic techniques and therefore, the width is limited in size.